-50%

UsedYield Modelling and Defect Tolerance in VLSI, Papers Presented at the INT Workshop on Designing for Yield, 1-3 July 1987, Oxford by Will Moore (Author), Wojciech Maly (Author), Andrzej J. Strojwas (Editor)

Name: UsedYield Modelling and Defect Tolerance in VLSI, Papers Presented at the INT Workshop on Designing for Yield, 1-3 July 1987, Oxford by Will Moore (Author), Wojciech Maly (Author), Andrzej J. Strojwas (Editor)
SKU: 12729
Price: 795.00 INR
Availability: InStock

₹795.00

1 in stock

Add to wishlist

Courier Delivery

Our courier will deliver to the specified address 2-7 Days

Free Shiping

Free shiping on order above ₹499

Payment Methods:

Description

Customer Reviews

Rated 0 out of 5

0 reviews

Rated 5 out of 5

0

Rated 4 out of 5

0

Rated 3 out of 5

0

Rated 2 out of 5

0

Rated 1 out of 5

0

Reviews

Clear filters

There are no reviews yet.

Be the first to review “UsedYield Modelling and Defect Tolerance in VLSI, Papers Presented at the INT Workshop on Designing for Yield, 1-3 July 1987, Oxford by Will Moore (Author), Wojciech Maly (Author), Andrzej J. Strojwas (Editor)”

Your email address will not be published. Required fields are marked *

Your rating *

Value for money

1 2 3 4 5

Durability

1 2 3 4 5

Delivery speed

1 2 3 4 5

Your review *