UsedYield Modelling and Defect Tolerance in VLSI, Papers Presented at the INT Workshop on Designing for Yield, 1-3 July 1987, Oxford by Will Moore (Author), Wojciech Maly (Author), Andrzej J. Strojwas (Editor)
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UsedYield Modelling and Defect Tolerance in VLSI, Papers Presented at the INT Workshop on Designing for Yield, 1-3 July 1987, Oxford by Will Moore (Author), Wojciech Maly (Author), Andrzej J. Strojwas (Editor)

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