(Used Book) Yield Modelling and Defect Tolerance in VLSI, Papers Presented at the INT Workshop on Designing for Yield, 8 by Will Moore (Author), Wojciech Maly (Author), Andrzej J. Strojwas
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(Used Book) Yield Modelling and Defect Tolerance in VLSI, Papers Presented at the INT Workshop on Designing for Yield, 8 by Will Moore (Author), Wojciech Maly (Author), Andrzej J. Strojwas

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